Modern integrated circuits utilize multiple layers of conductive material in the realization of the desired electronic circuit function. These layers often include diffusion regions in the semiconductor substrate, one or more layers of polysilicon interconnection, and a top metallization layer consisting of aluminum or an aluminum alloy. Because of the presence of these underlying conductive layers and also of the presence of isolation oxide in selected areas of the integrated circuit, the metallization layer generally must be deposited on a surface which has far from a planar topology, requiring each metal line to make steps over various topological features in order to carry current from one area of the device to another. A example of a worst case step could require a metal line to make a step over a coincident edge of two layers of polysilicon and an edge of a field oxide isolation layer. Furthermore, the metal lines must be connected to other conductive layers in order for the circuit to be capable of functionality; this may require a contact from the top metal line, over the two underlying polysilicon layers, all the way to a diffusion. The ability of a metallization layer to reliably cover steps, and to reliably make contacts, can be the limiting factors in the layout of an integrated circuit.
Currently, metallization layers are either evaporated or sputtered onto the surface of the semiconductor slice. Relative to the problem of step coverage, if a step to be made by the metal line (either evaporated or sputtered) is too steep, the deposited metal line may be broken over the step, causing the integrated circuit to be non-functional. Even for those circuits which function, the metal line is likely to be thinner in the location of the step than elsewhere in the circuit. It is well known that aluminum and aluminum-alloy metal lines are prone to electromigration failures within the useful life of the circuit if the current density is above a certain limit; the presence of steps which are too steep for the metallization technology will, due to the thinning over the step, provide sites for electromigration failures. Accordingly, from a yield and reliability standpoint, the steepness of the steps required of a metal line should be minimized.
Contact between a metal line and underlying layers is often made by way of etching holes in the oxide layer upon which the metal will be deposited, prior to metal deposition. These holes must open to the underlying layer to which connection is desired, whether diffusion, polysilicon, or both. Of course, the smaller the size of the contact, less surface area is required for the silicon realization of the circuit, not only for the contact area itself, but also to provide a safe area around the contact to prevent shorting of the metal line to a polysilicon line to which connection is not desired. However, as contacts are made smaller, the likelihood that the metallization may not completely fill the contact via and make good ohmic contact increases. In addition, since contact to different underlying layers is required, difficulty in controlling the etch of the oxide layer exists, since the time to etch to a diffusion will necessarily be longer than the time required to etch to a polysilicon layer above the surface of the slice. Tight process control is thus required in order to both allow contact to the diffusion and also to prevent the polysilicon contacts from becoming too large ("blowing out"). While an etch process may be used which will make the walls of the contact substantially vertical, the etch may also etch through the polysilicon of the upper layer before making contact to a lower layer such as a diffusion. In addition, using only an evaporation or sputtering of the metal layer after contact etch, a vertical walled contact may cause thinning and breaking problems as discussed above relative to step coverage may also occur in the contact via.
The engineer responsible for layout of the integrated circuit on silicon is thus given a number of restrictions in the routing of the metallization. For example, a minimum distance between an edge of first polysilicon and an edge of second polysilicon may be required to be maintained, which allows the metal line to be required to only make one step at a time. In addition, a minimum metal line width may be required in order for the current density of the metal line to be below the theshold limit for electromigration purposes, with the thinning effect of the metal as it makes a step taken into account. Since the thinning of the metal line over a step can be more than 50%, the metal line width will need to be accordingly widened by more than 50% to account for its thinning over the step. Relative to contacts, the layout engineer must keep unrelated polysilicon a minimum distance away from each contact via, while maintaining a reliable minimum contact size. Each of these minimum size and distance requirements cause the size of the silicon area necessary for the layout of the integrated circuit to increase, reducing the number of circuits on a given semiconductor slice, and increasing the cost of each circuit.
It is therefore an object of this invention to provide a process for manufacturing an integrated circuit which provides a planar surface for the top metallization interconnection layer.
It is a further object of this invention to provide such a planar surface while also providing uniformly sized contacts of different depths, thereby allowing the top metallization layer to contact conductive layers at differing depths.
Other objects of the invention will be apparent to those skilled in the art, and having reference to this specification.